In the manufacturing of Fin Field-Effect Transistors (FinFETs), fin heights often need to be extracted. In addition, the overlap capacitance values between gate electrodes of FinFETs and the underlying features such as Lightly Doped Drain/source (LDD) regions also need to be determined sometimes. Previously, the extraction of the fin heights includes forming samples that include fins having different fin heights, measuring the fin heights using Transmission Electron Microscope (TEM), and measuring the respective inversion capacitance of the fins. A mapping is thus formed to correlate the inversion capacitance values with the fins heights. When a fin height of a fin on a wafer needs to be determined, the determination of the fin height may be performed by measuring the inversion capacitance of the fin, and find out the respective fin height from the mapping. This method, however, suffers from the adverse effect of the parasitic capacitance from contact plugs and epitaxy regions, which parasitic capacitance is included in the measured inversion capacitance. Similarly, the overlap capacitance also suffers from the adverse effect of the respective parasitic capacitance.